Computer Hardware Engineering student at the University of Miami focused on FPGA design, semiconductor research,
and low-level systems engineering.
Currently conducting TRNG research at the NanoMagnetoElectronics Lab.
I'm a Computer Hardware Engineering student with a deep focus on digital hardware design and semiconductor research. My work spans from RTL design in Verilog and VHDL on real FPGA boards, to hands-on lab research involving optical magnetometry and true random number generation.
At the NanoMagnetoElectronics Lab, I design and operate an automated MOKE (Magneto-Optical Kerr Effect) measurement system, interfacing an SR865A lock-in amplifier with FPGA hardware over RS-232/PyVISA to characterize magnetic thin films. My senior design project — ARIS (Authenticated Randomness Infrastructure Service) — leverages this research to build a cryptographically auditable TRNG.
I'm also active in AI evaluation research, running structured benchmarks across Claude, ChatGPT, and Gemini to assess generative model performance on escalating hardware-engineering task complexity.
Outside of research: IEEE Student Member · Quantum Computing Learning Group · Hackathon Organizer & Planner ·
ARIS is a hardware-based True Random Number Generator (TRNG) that derives entropy from Magneto-Optical Kerr Effect (MOKE) hysteresis measurements of magnetic thin-film samples. The system integrates a Stanford Research SR865A dual-phase lock-in amplifier with FPGA processing to produce cryptographically auditable random bitstreams.
A structured 4-stage benchmarking study evaluating Claude, ChatGPT, and Gemini on hardware engineering tasks of escalating complexity — from basic RTL generation to multi-module FPGA system design. Evaluation is manual, assessing correctness, code structure, and integration quality.
Full VGA display system on DE1-SoC FPGA rendering a real-time drawing application at 1280×1024 @ 60 Hz. Implements a 3-state FSM (IDLE→READ→WRITE) with dual-port block RAM frame buffer and read-modify-write memory operations for glitch-free cursor rendering.
Ripple-carry adder/subtractor implemented in Verilog on the Nexys 4 DDR Artix-7 board with 7-segment display output, overflow detection, and validated against all 256 input combinations. Power report generated from Vivado.
16-to-32-bit barrel shifter on the DE1 board with 8-bit signed control code, HI/LO reference bit selection, and both sign-preserving and zero-fill shift modes. Implements ripple-carry structure with MUX-based selection and tristate buffers.
8-bit binary to 2-digit BCD converter driving a dual 7-segment LED display (range 0–99) with overflow detection logic. Pure combinational design implemented in VHDL.
8-bit arithmetic calculator implemented in VHDL supporting add, subtract, multiply, and divide operations with 7-segment display I/O on FPGA hardware.
Multi-project DSP series in VHDL. Project 1 complete: 7-segment hex display decoder (0–F, full behavioral case map). Projects 2–6 target FIR filtering, FFT, and signal analysis pipelines — releasing through April 2026.
Complete buffered I/O layer (mio) built in C implementing myopen / myread / mywrite / mygetc / mygets / mygetline / myflush / myclose
with configurable buffer sizes, three stream modes, and global STDIN/STDOUT/STDERR wrappers. Zero memory leaks
verified with Valgrind. Includes a fully functional ./ls implementation using
opendir/stat syscalls.
Reverse Polish Notation calculator in C++ with a custom arbitrary-precision integer class using a digit vector. Supports full operator set including compound assignment and factorial, stream I/O, string construction, and O(n) multiply. Tested on 20+ digit operands.
Dual-Tone Multi-Frequency signal generator in MATLAB producing standard telephone keypad tones by summing row and column frequency sinusoids, with spectral analysis and audio output.
Python implementation of the Nim game with an AI opponent using optimal strategy (Sprague-Grundy / Nim-sum theory). AI plays perfect strategy; human player can choose pile and remove count each turn.
C++ route mapping application implementing graph traversal algorithms for pathfinding. Reads map data, builds adjacency structures, and outputs optimal routes.
Backtracking solution to the N-Queens constraint satisfaction problem in Python. Finds all valid queen placements on an N×N board with configurable board size and solution display.